1. Technical Field
The embodiments described herein relate to a design of a semiconductor memory apparatus, and in particular, to a test circuit device for a semiconductor memory apparatus.
2. Related Art
As the capacity of semiconductor memory devices increases, the total number of individual memory cells within a given area of the semiconductor memory apparatus increases. Accordingly, the probability of a micro-bridge being established between adjacent word lines WL and bit lines BL increases.
FIG. 1 is a schematic circuit diagram of a conventional micro-bridge detection circuit of a semiconductor memory apparatus. In FIG. 1, a micro-bridge detection circuit 11 of a semiconductor memory apparatus includes a main word line driver 10, a local driver 20, a driving voltage supplying unit 30, and a sub word line driver 40.
The main word line driver 10 includes a first inverter circuit 11 that receives a main decoding signal ‘MDEC’ to supply a signal that swings between a driving voltage VPP and a ground voltage VSS to the sub-word line driver 40. The local driver 20 includes a second inverter 21 that receives a local decoding signal ‘LDEC’ to supply a signal that swings between the driving voltage VPP and the ground voltage VSS to the driving voltage supplying unit 30. The driving voltage supplying unit 30 receives an output signal ‘LDB’ from the local driver 20 and a word floating test mode signal ‘TWLFLOAT’, and supplies the driving voltage VPP as an output signal ‘LD’ to the sub-word line driver 40. The sub-word line driver 40 determines whether or not the sub-word line SWL is enabled in response to output signals ‘MWLB’, ‘LDB’, and ‘LD’ of the main word line driver 10, the local driver 20, and the driving voltage supplying unit 30, respectively.
The unit arrangement of FIG. 1 is configured by a plurality of cell arrays in accordance with the configuration of the memory apparatus. For purposes of explanation, the cell array of FIG. 1 is added to assist with describing operations of the micro-bridge detection circuit 1, and a minute bridge that is generated due to the presence of the micro-bridge between the word line and the bit line is schematically represented as a resistor MB.
FIG. 2 is a diagram representing conventional operation signals of a circuit according to the presence/absence of a micro-bridge. In FIGS. 1 and 2, in a state where data “0” is stored in a memory cell of a semiconductor memory apparatus at an initial stage, when an active command signal ‘ACT’ is input, the main decoding signal ‘MDEC’ and the local decoding signal ‘LDEC’ are enabled at a high level. The first inverter circuit 11 of the main word line driver 10, to which the main decoding signal ‘MDEC’ is input, supplies an output signal ‘MWLB’ that is enabled at a low level to the sub-word line 40. The second inverter circuit 21 of the local driver 20, to which the local decoding signal ‘LDEC’ is input, supplies an output signal ‘LDB’ that is enabled at a low level to the driving voltage supplying unit 30. In this case, the word line floating test mode signal ‘TWLFLOAT’ is maintained to be disabled at a low level. Thus, a PMOS transistor P2 that receives a low word line floating test mode signal ‘TWLFLOAT’ is turned ON, and the driving voltage supplying unit 30 that receives the output signal ‘LDB’ of the local driver, which is enabled at a low level, supplies the driving voltage VPP to the sub-word line driver 40.
The sub-word line driver 40 causes the sub-word line SWL to be enabled in response to the output signal ‘MWLB’ of the main word line driver 10 that is enabled at a low level and the output signal ‘LDB’ of the driving voltage supplying unit 30. When the sub-word line SWL is enabled, a bit line and a bit (bar) BL line are amplified by a bit line sense amplifier. In addition, after the charge sharing operation, data “0” is stored in the memory cell node. In this case, if the word line floating test mode signal ‘TWLFLOAT’ is enabled at a high level, then the PMOS transistor P2 of the driving voltage supplying unit 30 that receives the word line floating test mode signal ‘TWLFLOAT’ through a gate terminal is turned OFF. Thus, the driving voltage VPP that is supplied to the sub-word line driver 40 is intercepted and the sub-word line SWL is in a floating state. If the floating state is maintained for a long time period, the micro-bridge MB is generated between the sub-word line and the bit line so that the level of the sub-word line SWL is reduced to the ground voltage VSS level. Specifically, a current path is generated from the sub-word line SWL to the bit line so that the level of the sub-word line SWL is reduced to the ground voltage VSS level.
In the floating state, if data “1” is intended to be written into a memory cell by a write command, then the data “1” is transmitted to the bit line. However, since the level of the sub-word line SWL is reduced to the ground voltage level VSS, the memory cell node cannot store the data “1”, and instead holds data “0”. After completing the write operation, if the precharge command PCG is performed, then the word line floating test mode signal ‘TWLFLOAT’ is disabled. Next, when the active command is input again, the memory cell fails to read the data “1”, and thus, indicates that the micro-bridge MB is present. In contrast, if the micro-bridge MB is not present, then the sub-word line SWL is maintained at the driving voltage VPP level. Thus, the data “1” can be successfully stored in the memory cell.
However, although the first, second, and third NMOS transistors N1, N2, and N3 are turned OFF when the sub-word line SWL is enabled, a leakage current exists due to the characteristics of the first, second, and third NMOS transistors N1, N2, and N3 in the turned OFF state. Thus, even when the micro-bridge MB is not present, the level of the sub-word line SWL will be reduced to the ground voltage VSS level due to the leakage current. For example, since the leakage current caused by the NMOS transistors N1, N2, and N3 causes the level of the sub-word line SWL to be reduced to the ground voltage level VSS, even in a normal state when the micro-bridge MB is not present, it may be recognized that the micro-bridge MB is present, thereby making it difficult to exactly detect the presence of the micro-bridge MB.